Manufacturers of a system on chip (SoC) are sensitive to the need to improve the energy efficiency of such devices. Various measures may be taken to reduce power consumption, such as operating at a lower voltage. For a low power SoC, a configurable SRAM operating at low voltage is a key component.
As these devices are scaled, the low-voltage functionality of high density SRAMS has been compromised. Increased threshold-voltage variation of scaled transistors reduces the static noise margin (SNM) and write margin (WM) of the SRAM bit cell. The effect is more predominant for high-density SRAMs due to small device sizes and large memory capacity requirements.
Moreover, lower voltages typically reduce the speed at which signals propagate through the memory. Transistor delays and RC delays associated with a memory scale differently as the voltage is lowered. Consequently, the memory may not operate as fast as needed or desired.
Voltage scaling is used to ensure reliability of the memory and to ensure a reduced power consumption. Voltage scaling is a technique whereby the drive voltage to a particular part of the memory is modulated to one or more particular values such that the memory can function properly. Voltage scaling is particularly suited to compensate for process variations. Static voltage scaling may be performed at the factory (e.g., during calibration), or before the memory begins normal operation (e.g., during power-up initialization). In contrast, dynamic voltage scaling (DVS) is performed continually while the memory is in normal operation, and is particularly effective at compensating for temperature variations and memory aging as well as process variations.
As the voltage is lowered, an influence of variations in various manufacturing parameters increases, and may cause large variations in the threshold voltage of the transistors that form a memory cell. Consequently, it becomes difficult to perform stable writing and reading of data in a memory with a low power supply voltage.
Signals that propagate too slowly through the memory cause setup violations. Signals that propagate too quickly through the memory cause hold violations. Setup or hold violations corrupt the flow of logic and give rise to functional errors.
Various structures have been proposed for stably writing and reading data in a memory with such a low power supply voltage. For example, U.S. Pat. No. 8,301,883 discloses a driver power supply circuit stepping down a power supply voltage at a power supply node of a word line driver. The driver power supply circuit includes a resistance element and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
Another approach is based on a constant-negative-level write buffer (CNL-WB) and a level programmable wordline driver for single supply (LEWD-SS) operation, as disclosed in the article titled “A Configurable SRAM with Constant-Negative-Level Write Buffer for Low-voltage Operation with 0.149 μm2 Cell in 32 nm High-k Metal-Gate CMOS”, IEEE International Solid-State Circuits Conference, 2010, pp. 348-350. The CNL-WB uses a bootstrap circuit by automatically adjusting the BL bias to an optimized constant negative level. The amount of charge stored in the bootstrap capacitor is automatically controlled depending on the number of rows. To generate a constant BL level, the additional charge stored in the capacitor is proportional to the BL capacitance increase.
Yet another approach is based on a partially suppressed wordline (PSWL) scheme for read assist and a bitline-length-tracked negative-bitline-boosting (BT-NBL) scheme for write assist, as disclosed in the article titled “A 20 nm 112 Mb SRAM in High-k Metal-Gate with Assist Circuitry for Low-Leakage and Low-Vmin Applications”, IEEE International Solid-State Circuits Conference, 2013, pp. 316-318. Since the negative bitline coupling time is crucial for the negative bias coupling efficiency, a replica column with a replica write buffer tracks the SRAM bitline configuration. During the write operation, the write signal pulse triggers the replica write buffer of the replica column to discharge the replica bitline to generate a negative bitline enable signal. The falling edge of the selected bitline through a write driver and the write column-MUX to increase the gate-source bias of the selected bitcell pass-gate transistor enhances the write capability.
Even in view of the above approaches for operating a memory at low voltage, there is still a need to improve on providing the proper assist to the memory.